An insulated-gated field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located within a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and the drain are formed by introducing dopants of a second conductivity type (P or N) into a semiconductor substrate of a first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also known as polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anistropically etched to provide a gate that provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 volts), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For example, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator, causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). An LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source--unless bidirectional current is used--however, lightly doped regions are typically formed for both the source and the drain to avoid additional processing steps.
The formation of spacers to create a graded dopant profile within the source and the drain, as found in the prior art, is disadvantageous in that it does not permit control over the graded dopant profile--and thus corresponding performance and reliability characteristics of the IGFET itself. The dopant profile mirrors the profile of the spacer, which as found in the prior art is usually limited to a circular shape, which is less than ideal to form a true graded dopant profile. Furthermore, prior art formation of spacers requires doping of the source and the drain in two separate processing steps--a first step to lightly dope the drain (and correspondingly, the source), and a second step to more heavily dope the drain and the source regions. Thus, prior art formation of spacers suffers from less controllable dopant profiles and complexity in the number of processing steps needed to dope the source and drain regions of an IGFET.
Another problem with prior art IGFETs specific to salicide-gate MOSFETs is the closeness of the metal silicide layers over highly doped regions to the metal silicide layer over the polysilicon gate. This may result in undesirable electrical fields between these regions. In a salicide-gate MOSFET, typically the metal silicide is formed within the highly doped regions immediately adjacent to the spacers used to form the underlying lightly doped regions. That is, the spacers used to form the underlying lightly doped regions also define the placement of metal silicide within the highly doped region. To further distance the metal silicide within the highly doped regions from the polysilicon gate, these spacers themselves would have to be widened. However, widening the spacers may affect the performance and reliability characteristics of the IGFET itself. Thus, prior art formation of metal silicide within the highly doped regions may result in difficult and perhaps unsolvable design issues for semiconductor designers.